![PDF] A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/5c91574c88acf49f9324c22db821eb330fc62afc/9-Figure11-1.png "PDF] A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell | Semantic Scholar")
PDF] A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell | Semantic Scholar
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